Digital India RISC-V Microprocessor (DIR-V) Program launched

To achieve commercial silicon and design wins for the next generation microprocessors by December 2023, the Government of India on Wednesday announced the launch of Digital India RISC-V (DIR-V) program. RISC-V is a free and open ISA enabling a new era of processor innovation through open standard collaboration.

The government initiative is pegged to be another concrete step towards realizing the ambition of self-reliance towards “Atmanirbhar Bharat”.

While setting the aggressive milestones for commercial silicon of SHAKTI & VEGA and their design wins by December 2023, Minister of State for Electronics & Information Technology and Skill Development & Entrepreneurship Rajeev Chandrasekhar mentioned that DIR-V will see partnerships between Startups, Academia & Multinationals, to make India not only a RISC-V Talent Hub for the World but also supplier of RISC-V SoC (System on Chips) for Servers, Mobile devices, Automotive, IoT & Microcontrollers across the globe.

While speaking with the media, Chandrasekhar recalled his early days as x-86 processor chip designer at Intel and mentioned that many new processor architectures have gone through an initial period of ferment characterized by waves of innovations. At some point, however, they all settled on a dominant design.

ARM and x-86 are two such instruction set architectures- one of which is licensed and other is sold, where industry consolidated in earlier decades.

However, RISC-V has emerged as a strong alternative to them in last decade, having no licensing encumbrances, enabling its adoption by one and all in semiconductor industry, at different complexity levels for various design purposes,

Challenging the status quo, RISC-V Instruction Set Architecture (ISA)

The Ministry of Electronics and IT (MeitY) is also planning to join the RISC-V International as Premiere Board Member to collaborate, contribute and advocate India’s expertise with other global RISC-V leaders.

Professor V. Kamakoti, Director, IIT Madras will be the Chief Architect and S. Krishnakumar Rao as Program Manager of DIR-V Program. Minister Chandrasen also unveiled the Blueprint of the roadmap of design & implementation of the DIR-V Program with – SHAKTI Processor by IIT Madras and VEGA Processor by C-DAC along with the strategic Roadmap for India’s Semiconductor Design & Innovation to catalyze the semiconductor ecosystem in the country.


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